The transmission of a digital signal over a noisy channel generally comprises the use of an error correction code so as to obtain a bit error rate (BER) or block error rate (also frame error rate, FER) which is acceptable even with a small signal-to-noise ratio. As a general rule, the decoding operation is more complex than the coding operation in terms of computation time and equally in terms of memory, and hence of area of silicon occupied.
Among the various coding and decoding algorithms which have been developed, iterative codes, such as “turbo codes”, have acquired great significance in the last few years. These codes are described, for example, in the following articles:                “Near Shannon limit error-correcting coding and decoding: Turbo codes”, P. Thitimajshima, C. Berrou, A Glavieux, IEEE ICC 93, pages 1064-1070, 1993 Geneva; and        “Near-optimum decoding of product codes: Block turbo codes”, R. M. Pyndiah, IEEE Transactions on Communications, 46(8): 1003-1010, 1998;as well as in European patent EP 0 753 696 and in international application WO 01/06661.        
“Turbo” codes are obtained by parallel concatenation of convolutional codes; codes obtained by series concatenation of convolutional codes, which have similar properties and also constitute a field of application of the present invention are known as “turbo-like” codes.
These codes are characterized by the fact that the decoding is an iterative procedure and the BER and the FER decrease at each iteration. Often the number Nit of iterations is fixed and it is determined by considering the case of the blocks that are most corrupted by noise. It is obvious that this entails a waste of resources, since most blocks undergo more iterations than necessary. For this reason stopping rules have been envisaged; see in this regard:                “Stopping rules for turbo decoders” F. Pollara, A. Matache, S. Dolinar, Technical Report 42-142, TMO Progress Report, August 2000; and        “A simple stopping criterion for turbo decoding” W. J. Ebel, Y. Wu, B. D. Woermer, IEEE Communications Letters, 4(8): 258-260 (2000).        
To increase the data bit rate, use is typically made of decoders consisting of several replicas of the same decoding module, each module taking charge of the processing of a block of bits. Disregarding problems related to multiplexing on input and to demultiplexing on output, the bit rate is proportional to the number M of modules used. There are essentially three architectures based on this principle: the pipeline architecture, the parallel architecture and the matrix architecture, which are illustrated by FIGS. 1A, 1B and 1C respectively.
In the pipeline architecture, M=Nit modules are connected in series as in an assembly line. A block of bits introduced at the input of the line exits same after having been processed once by each module, hence after having undergone Nit iterations.
In the parallel architecture, M modules each perform the complete decoding (Nit iterations) of a block of bits. It is easy to appreciate that if M=Nit the performance of a parallel decoder is the same as that of a pipeline decoder, both in terms of complexity and bit rate. If M>Nit, the bit rate is higher, but so is the complexity, whereas the reverse effect is obtained for M<Nit. Here and subsequently in this document, the term “complexity” is understood to mean a quantity proportional to the area occupied on an electronic chip by a circuit embodying the decoder. Complexity depends both on the architecture of the decoder and on the microelectronic technology chosen; for a given technology, the complexity makes it possible to compare various architectures.
The matrix architecture is merely a generalization of the previous two: a matrix decoder is composed of M pipeline decoders in parallel.
These architectures are essentially equivalent and the choice to use one rather than another depends on considerations specific to the application considered. A decoder based on any one of them can operate only for a fixed number of iterations, this entailing a waste of hardware resources and a higher than necessary energy consumption.
More recently, modular decoder architectures allowing the application of stopping rules have been developed.
Document DE 102 14 393, which represents the closest state of the art, discloses an iterative decoder comprising a plurality of servers, each iteratively decoding a data block, an input buffer including more memory locations than servers and a control unit for allocating data packets stored in the input buffer to the different servers.
Document WO 02/067435 A1 describes a decoder comprising a plurality of decoding modules in parallel and a device for dynamically allocating incoming data packets. Although the allocating device is equipped with a temporary memory, the decoder is designed in such a way that the probability of an incoming data packet not finding any free decoding module is small. In order for this condition to hold, it is necessary to use a large number of modules, of which at least one will not be busy almost at each instant. This therefore results in a waste of hardware resources. Moreover, this document provides no information which makes it possible to determine the number of decoding modules and of elements of the temporary memory as a function of the performance required and of the operating conditions of the decoder.
Document EP 0 973 292 A2 describes the use of a buffer memory for each decoding module (also called a “server”), so as to produce as many queues as modules, plus possibly a global buffer memory at the level of the allocating device. In this document the use of a stopping criterion is not described: on the contrary, the number of iterations is determined a priori on the basis of the ratio of the power of the carrier to that of the noise. While this ratio remains constant, the duration of the decoding is the same for all the packets: there is therefore the same problem of overdimensioning encountered in the architectures with a fixed number of iterations described above.